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PCK2000 CK97 (66/100MHz) System Clock Generator
Product specification 1998 Sep 29
Philips Semiconductors
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
FEATURES
* Mixed 2.5V and 3.3V operation * Four CPU clocks at 2.5V * Eight synchronous PCI clocks at 3.3V, one free-running * Two 2.5V IOAPIC clocks @ 14.318 MHz * Two 3.3V 48MHz USB clock outputs * Three 3.3V reference clocks @ 14.318 MHz * Reference 14.31818 MHz Xtal oscillator input * 100 MHz or 66 MHz operation * Part provides frequencies for Pentium Pro and
Pentium IITM motherboards
PIN CONFIGURATION
1 2 3 4 5 6 7 8 48 47 46 45 44 43 42 41 40 39
REF0 REF1 VSSREF XTAL_IN XTAL_OUT VSSPCI0 PCICLK_F PCICLK1
VDDREF REF2 VDDAPIC IOAPIC0 IOAPIC1 VSSAPIC RESERVED VDDCPU0 CPUCLK0 CPUCLK1 VSSCPU0 VDDCPU1 CPUCLK2 CPUCLK3 VSSCPU1 VDDCORE1 VSSCORE1 PCISTOP CPUSTOP PWRDWN RESERVED SEL0 SEL1 SEL100/66
VDDPCI0 9 PCICLK2 10 PCICLK3 11 VSSPCI1 12 PCICLK4 13 PCICLK5 14 VDDPCI1 15 PCICLK6 16 PCICLK7 17 VSSPCI2 18
* Power management control input pins * 175 ps CPU clock jitter * 175 ps skew on outputs * 1.5 - 4 ns CPU-PCI delay * Power down if PWRDWN is held LOW * Available in 48-pin SSOP package * See PCK2000M for 28-pin mobile version
DESCRIPTION
The PCK2000 is a clock synthesizer/driver chip for a Pentium Pro or other similar processors. The PCK2000 has four CPU clock outputs at 2.5V. There are eight PCI clock outputs running at 33MHz. One of the PCI clock outputs is free-running. Additionally, the part has two 3.3V USB clock outputs at 48MHz, two 2.5V IOAPIC clock outputs at 14.318MHz, and three 3.3V reference clock outputs at 14.318MHz. All clock outputs meet Intel's drive strength, rise/fall time, jitter, accuracy, and skew requirements. The part possesses dedicated powerdown, CPUSTOP, and PCISTOP input pins for power management control. These inputs are synchronized on-chip and ensure glitch-free output transitions. When the CPUSTOP input is asserted, the CPU clock outputs are driven LOW. When the PCISTOP input is asserted, the PCI clock outputs are driven LOW, except for free running PCICLK_F clock output.. Finally, when the PWRDWN input pin is asserted, the internal reference oscillator and PLLs are shut down, and all outputs are driven LOW. The PCK2000 is available in a 48-pin SSOP package.
PCK2000
38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDCORE0 19 VSSCORE0 20 VDD48MHz 21 48MHz0 22 48MHz1 23 VSS48MHz 24
SW00237
ORDERING INFORMATION
PACKAGES 48-Pin Plastic SSOP TEMPERATURE RANGE 0C to +70C OUTSIDE NORTH AMERICA PCK2000 DL NORTH AMERICA PCK2000 DL DRAWING NUMBER SOT370-1
Intel and Pentium are registered trademarks of Intel Corporation.
1998 Sep 29
2
853-2129 20102
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
PIN DESCRIPTION
PIN NUMBER 1, 2, 47 3 48 4 5 6, 12, 18 7 9, 15 8, 10, 11, 13, 14, 16, 17 19, 33 20, 32 21 24 22, 23 26, 27 25 29 30 31 37, 41 34, 38 35, 36, 39, 40 43 46 44, 45 28, 42 SYMBOL REF [0-2] VSSREF VDDREF XTAL_IN XTAL_OUT VSSPCI [0-2] PCICLK_F VDDPCI [0-1] PCICLK [1-7] VDDCORE [0-1] VSSCORE [0-1] VDD 48MHz VSS 48MHz 48MHz [0-1] SEL0,1 SEL100/66 PWRDWN CPUSTOP PCISTOP VDDCPU [0-1] VSSCPU [0-1] CPUCLK [0-3] VSSAPIC VDDAPIC IOAPIC [0-1] RESERVED 14.318 MHz clock outputs GROUND for REF outputs POWER for REF outputs 14.318 MHz crystal input 14.318 MHz crystal output GROUND for PCI outputs Free-running PCI output POWER for PCI outputs PCI clock outputs. Isolated POWER for core Isolated GROUND for core POWER for 48MHz outputs GROUND for 48MHz outputs 48MHz outputs Logic select pins. Select pin for enabling 66 MHz or 100MHz. L = 66 MHz H = 100MHz Control pin to put device in powerdown state, active low Control pin to disable CPU clocks, active low Control pin to disable PCI clocks, active low POWER for CPU outputs GROUND for CPU outputs CPU clock outputs @2.5V GROUND for IOAPIC outputs POWER for IOAPIC outputs IOAPIC output @ 2.5V Reserved for future use FUNCTION
NOTES: 1. VDD and VSS names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on the performance of the device. In reality, the platform will be configured with the VDDAPIC and VDDCPU pins tied to a 2.5V supply, all remaining VDD pins tied to a common 3.3V supply and all VSS pins being common.
1998 Sep 29
3
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
BLOCK DIAGRAM
X REFCLK [0-2](14.318 MHz) PWRDWN LOGIC X IOAPIC [0-1](14.318 MHz) XTAL_IN X 14.318 MHZ OSC PLL2
XTAL_OUT X
PWRDWN LOGIC
X 48MHz [0-1](48MHz)
PLL1
STOP LOGIC
X CPUCLK [0-3] (100MHz/66MHz)
SEL0 X SEL1 X SEL100/66 X LOGIC
PWRDWN LOGIC
X PCICLK_F (33MHz)
STOP LOGIC CPUSTOP X PCISTOP X PWRDWN X
X PCICLK [1-7](33MHz)
SW00236
SELECT FUNCTIONS
SEL100/66 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 FUNCTION TRI-State Reserved Reserved Active 66MHz Test mode Reserved Reserved Active 100MHz 1 NOTES 1
NOTE: 1. Internal decode logic for all three select inputs implemented.
FUNCTION DESCRIPTION 3-STATE TEST MODE
OUTPUTS CPU HI-Z TCLK/2 PCI, PCI_F HI-Z TCLK/6 48MHz HI-Z TCLK/2 REF HI-Z TCLK IOAPIC HI-Z TCLK NOTES
NOTE: 1. TCLK is a test clock driven in on the XTAL_IN input in Test Mode.
1998 Sep 29
4
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
FUNCTION TABLE
SEL 100/66 0 1 CPU/PCI RATIO 2 3 CPUCLK (0-3) (MHz) 66.66 100 CPICLK (1-7) PCICLK_F (MHz) 33.33 33.33 REF (0-2) IOAPIC (0-1) (MHz) 14.318 14.318 48MHz (0-1) 48 48
CLOCK ENABLE CONFIGURATION
CPUSTOP X 0 0 1 1 PCISTOP X 0 1 0 1 PWRDWN 0 1 1 1 1 CPUCLK LOW LOW LOW 100/66MHz 100/66MHz PCICLK LOW LOW 33MHz LOW 33MHz PCICLK_F LOW 33MHz 33MHz 33MHz 33MHz OTHER CLOCKS Stopped Running Running Running Running PLLs OFF Running Running Running Running OSCILLATOR OFF Running Running Running Running
POWER MANAGEMENT REQUIREMENTS
LATENCY SIGNAL SIGNAL STATE NO. OF RISING EDGES OF FREE RUNNING PCICLK 1 1 1 1 3ms 2 MAX
CPUSTOP
0 (DISABLED) 1 (ENABLED)
PCISTOP
0 (DISABLED) 1 (ENABLED)
PWRDWN
1 (NORMAL OPERATION) 0 (POWER DOWN)
NOTES: 1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the first valid clock that comes out of the device. 2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
1998 Sep 29
5
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to VSS (VSS = 0V) SYMBOL VDD3 VDDQ3 VDDQ2 IIK VI IOK VO IO TSTG PTOT PARAMETER DC 3.3V core supply voltage DC 3.3V I/O supply voltage DC 2.5V I/O supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current Storage temperature range Power dissipation per package plastic medium-shrink (SSOP) For temperature range: -40 to +125C above +55C derate linearly with 11.3mW/K VI < 0 Note 2 VO > VCC or VO < 0 Note 2 VO >= 0 to VCC -65 -0.5 -0.5 CONDITION LIMITS MIN -0.5 -0.5 -0.5 MAX +4.6 +4.6 +3.6 -50 5.5 50 VCC + 0.5 50 +150 850 UNIT V V V mA V mA V mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VDD3 VDDQ3 VDDQ2 VI VO Tamb PARAMETER DC 3.3V core supply voltage DC 3.3V I/O supply voltage DC 2.5V I/O supply voltage DC input voltage range DC output voltage range Operating ambient temperature range in free air CONDITIONS MIN Note 1 Note 2 Note 3 3.135 3.135 2.135 0 0 0 MAX 3.465 3.465 2.625 VDD3 VDDQ2 VDDQ3 +70 V V V V V C UNIT
NOTES: 1. VDD3 = VDDCORE1 = VDDCORE2 = 3.3V 2. VDDQ3 = VDDREF = VDDPCI0 = VDDPCI1= VDD48MHz = 3.3V 3. VDDQ2 = VDDAPIC = VDDCPU0 = VDDCPU1 = 2.5V
1998 Sep 29
6
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
DC CHARACTERISTICS
TEST CONDITIONS SYMBOL PARAMETER VDD (V) VIH VIL VOH2 VOL2 VOH3 VOL3 VPOH VPOL IOH IOH IOH IOH IOL IOL IOL IOL II IOZ Cin Cxtal Cout Idd3 HIGH level input voltage LOW level input voltage 2.5V output HIGH voltage CPUCLK, IOAPIC 2.5V output LOW voltage CPUCLK, IOAPIC 3.3V output HIGH voltage REF, 48MHz 3.3V output LOW voltage REF, 48MHz PCI output HIGH voltage PCI output LOW voltage CPUCLK output HIGH current IOAPIC output HIGH current 48MHz, REF output HIGH current PCI output HIGH current CPUCLK output LOW current IOAPIC output LOW current 48MHz, REF output LOW current PCI output LOW current Input leakage current 3-State output OFF-State current Input pin capacitance Xtal pin capacitance, as seen by external crystal Output pin capacitance O erating su ly Operating supply current Powerdown supply current Idd2 O erating su ly Operating supply current Powerdown supply current 2.625 66MHz mode 3.465 100MHz mode 66MHz mode 100MHz mode Outputs loaded1 Outputs loaded1 Output loaded1 Output loaded1 18 6 170 170 500 72 100 100 3.135 to 3.465 3.135 to 3.465 2.375 to 2.625 2.375 to 2.625 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 2.375 2.625 2.375 2.625 3.135 3.465 3.135 3.465 2.375 2.625 2.375 2.625 3.135 3.465 3.135 3.465 3.465 3.465 VOUT = Vdd or GND IO = 0 IOH = -1mA IOL = 1mA IOH = -1mA IOL = 1mA IOH = -1mA IOL= 1mA VOUT = 1.0V VOUT = 2.375V VOUT = 1.4V VOUT = 2.5V VOUT = 1.0V VOUT = 3.135V VOUT = 1.0V VOUT = 3.135V VOUT = 1.2V VOUT = 0.3V VOUT = 1.0V VOUT = 0.2V VOUT = 1.95V VOUT = 0.4V VOUT = 1.95V VOUT = 0.4V OTHER VDDQ2 = 2.5V 5% VDDQ3 = 3.3V 5% VDDQ3 = 3.3V 5% LIMITS Tamb = 0C to +70C MIN 2.0 VSS - 0.3 2.0 - 2.0 - 2.4 - -27 - -36 - -29 - -33 - 27 - 36 - 29 - 30 - - - TYP MAX VDD + 0.3 0.8 - 0.4 - 0.4 - 0.55 - -27 - -21 - -23 - -33 - 30 - 31 - 27 - 38 5 10 5 V V V V V V V V mA mA mA mA mA mA mA mA A A pF pF pF mA mA A mA mA A UNIT
All static inputs to VDD or GND
All static inputs to VDD or GND
NOTE: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section.
1998 Sep 29
7
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
AC CHARACTERISTICS
VDDREF = VDDPCI (0-1) = VDD48MHz = 3.3V 5%; VDDAPIC = VDDCPU (0-1) = 2.5V 5%; fcrystal = 14.31818 MHz
CPU CLOCK OUTPUTS, CPU(0-3) (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL THKP (tP) THKH (tH) THKL (tL) THKP (tP) THKH (tH) THKL (tL) THRISE (tR) THFALL (tF) TJITTER (tJC) DUTY CYCLE (tD) THSKW (tSK) THSTB (fST) PARAMETER CPUCLK period CPUCLK HIGH time CPUCLK LOW time CPUCLK period CPUCLK HIGH time CPUCLK LOW time CPUCLK rise time CPUCLK fall time CPUCLK jitter Output Duty Cycle CPU Bus CLK skew CPUCLK stabilization from Power-up 1 2 7 45 100MHz 66MHz TEST CONDITIONS NOTES 2 1, 5 1, 5 2 1, 5 1, 5 9 9 LIMITS Tamb = 0C to +70C MIN 15.0 5.2 5.0 10.0 3.0 2.8 0.4 0.4 1.6 1.6 175 55 175 3 ns ns ps % ps ms 10.5 ns MAX 15.5 ns UNIT
PCI CLOCK OUTPUTS, PCI(0-7) (LUMP CAPACITANCE TEST LOAD = 30pF)
SYMBOL TPKP (tP) TPKPS TPKH (tH) TPKL (tL) THRISE (tR) THFALL (tF) TPSKW (tSK) THPOFFSET (tO) TPSTB (fST) PARAMETER PCICLK period PCICLK period stability PCICLK HIGH time PCICLK LOW time PCICLK rise time PCICLK fall time PCI Bus CLK skew CPUCLK to PCICLK Offset PCICLK stabilization from Power-up TEST CONDITIONS NOTES 3 8 1 1 10 10 2 2, 4 7 1.5 12.0 12.0 0.5 0.5 2.0 2.0 500 4.0 3 LIMITS Tamb = 0C to +70C MIN 30.0 500 MAX ns ps ns ns ns ns ps ns ms UNIT
APIC(0-1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL PARAMETER TEST CONDITIONS NOTES f THRISE (tR) THFALL (tF) DUTY CYCLE (tD) THSTB (fST) Frequency, Actual Output rise edge rate Output fall edge rate Duty Cycle Frequency stabilization from Power-up (cold start) Frequency generated by Crystal 1 1 45 LIMITS Tamb = 0C to +70C MIN MAX MHz 4 4 55 3 ns ns % ms UNIT
14.31818
1998 Sep 29
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Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
REF(0-2) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL PARAMETER TEST CONDITIONS NOTES f THRISE (tR) THFALL (tF) DUTY CYCLE (tD) THSTB (fST) Frequency, Actual Output rise edge rate Output fall edge rate Duty Cycle Frequency stabilization from Power-up (cold start) Frequency generated by Crystal 1 1 45 LIMITS Tamb = 0C to +70C MIN MAX MHz 4 4 55 3 ns ns % ms UNIT
14.31818
48MHZ(0-1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL PARAMETER TEST CONDITIONS NOTES f fD THRISE (tR) THFALL (tF) DUTY CYCLE (tD) THSTB (fST) Frequency, Actual Devation from 48MHz Output rise edge rate Output fall edge rate Duty Cycle Frequency stabilization from Power-up (cold start) Determined by PLL divider ratio (48.008 - 48)/48 1 1 45 LIMITS Tamb = 0C to +70C MIN 48.008 +167 4 4 55 3 MAX MHz ppm ns ns % ms UNIT
ALL CLOCK OUTPUTS
SYMBOL TPZL, TPZH TPLZ, TPHZ PARAMETER Output enable time Output disable time TEST CONDITIONS NOTES LIMITS Tamb = 0C to +70C MIN 1.0 1.0 MAX 8.0 8.0 ns ns UNIT
NOTES: 1. See Figure 3 for measure points. 2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks. 3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz. 4. The CPUCLK must always lead the PCICLK as shown in Figure 2. 5. THKH is measured @ 2.0V as shown in Figure 4. 6. THKL is measured @ 0.4V as shown in Figure 4. 7. The time is specified from when VDDQ achieves its nominal operating level (typical condition is VDDQ = 3.3V) until the frequency output is stable and operating within specification. 8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified. 9. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.0V (1mA) JEDEC specification. 10. THRISE and THFALL (48MHz, REF, PC) are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V
1998 Sep 29
9
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
AC WAVEFORMS
VM = 1.25V @ VDDQ2 and 1.5V @ VDDQ3 VX = VOL + 0.3V VY = VOH -0.3V VOL and VOH are the typical output voltage drop that occur with the output load.
VI SEL 100, 66, SEL1, SEL0 GND VDDQ2 1.25V CPUCLK VSS VDD OUTPUT LOW-to-OFF OFF-to-LOW VX VDDQ2 1.25V CPUCLK VSS VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VY VM VOL tPHZ tPZH VM VM
tPLZ
tPZL
THSKW
SW00240
VSS
Figure 1. CPUCLK to CPUCLK skew
outputs enabled
outputs disabled
outputs enabled
SW00239
Figure 4. 3-State enable and disable times.
VDDQ2 1.25V CPUCLK VSS
COMPONENT MEASUREMENT POINTS 2.5VOLT MEASURE POINTS
VDDQ3 1.5V PCICLK VSS
VOH = 2.0V
VDDQ2 VIH = 1.7V 1.25V VIL = 0.7V
SYSTEM MEASUREMENT POINTS
VOL = 0.4V VSS
THPOFFSET
SW00241
COMPONENT MEASUREMENT POINTS 3.3VOLT MEASURE POINTS
Figure 2. CPUCLK to PCICLK offset
VOH = 2.4V
VOL = 0.4V THKP DUTY CYCLE THKH
2.5V CLOCKING INTERFACE 2.0 1.25 0.4
VDDQ3 VIH = 2.0V 1.5V VIL = 0.7V
SYSTEM MEASUREMENT POINTS
VSS
SW00243
Figure 5. Component versus system measure points
THKL TRISE TFALL TPKP TPKH
3.3V CLOCKING INTERFACE (TTL)
2.4 1.5 0.4
TPKL TRISE TFALL
SW00242
Figure 3. 2.5V/3.3V Clock waveforms
1998 Sep 29
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Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
CPUSTOP
CPUCLK (INTERNAL)
PCICLK (INTERNAL)
PCICLK (FREE-RUNNING)
CPUSTOP
CPUCLK (EXTERNAL)
PCISTOP
CPUCLK (INTERNAL)
PCICLK (INTERNAL)
PCICLK (FREE-RUNNING)
PCISTOP
PCICLK (EXTERNAL)
PWRDWN
CPUCLK (INTERNAL)
PCICLK (INTERNAL)
PWRDWN
CPUCLK (EXTERNAL)
PCICLK (EXTERNAL)
VCO
CRYSTAL
Figure 6. Power Management
1998 Sep 29
11
A A A A
SW00244
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
1998 Sep 29
12
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
NOTES
1998 Sep 29
13
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04605
Philips Semiconductors
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